| » Domain - Front End:
Engineers in this domain have qualifications and experience in Design Specification HDL Coding (VHDL/VERILOG), Logical Optimization, Functional Simulation(Gate level) and Synthesis (Netlist).
Tools:
» Mentor graphics ModelSim » Xilinx » Leonardo Spectrum » Design Compiler (Synopsis)
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» Domain - Back End:
Engineers in Back End have experience in Schematic entry Transistor level simulation Floor Planning (Placement & Routing) Circuit Extraction Layout Design Spice Extraction Fabrication.
Tools:
» Cadence » Synopsis » IC Station (Layout Editor) » H-Spice (Circuit Simulator)
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